[WIP] 3D Placement Constraints

verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

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This PR enhances the supoort for 3D placement constraints to allow the user to specify a layer range for each floorplanning constraint.

Related Issue

Motivation and Context

Each floorplan constraint is limited to a single layer. If the user wants to define a cubic floorplan constraint, she/he has to define multiple rectangular floorplan constraint with the same (x,y) coordinates but for different layers. This PR lets user defne a single floorplan region spanning across multiple layers.

How Has This Been Tested?

Types of changes

[ ] Bug fix (change which fixes an issue)
[x] New feature (change which adds functionality)
[ ] Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

[ ] My change requires a change to the documentation
[ ] I have updated the documentation accordingly
[ ] I have added tests to cover my changes
[ ] All new and existing tests passed

The FASM unit test failure seems to be due to a change in the default layers returned for placement constraints on a 2D device: 2024-06-24T20:23:40.5141020Z [0m[0;37m/home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing/vpr/test/test_vpr_constraints.cpp:51: [0m[1;31mFAILED: 2024-06-24T20:23:40.5143053Z [0m[0;36m REQUIRE( def_region.get_region_bounds().get_layer_range() == std::make_pair(-1, -1) ) 2024-06-24T20:23:40.5144059Z [0mwith expansion: 2024-06-24T20:23:40.5144514Z [1;33m {?} == {?}

Updating the REQUIRE to pair(0,0) should work.

@soheilshahrouz also tells me that if we make a custom printer class/method for std::pair catch2 will print objects instead of {?} in the failure.

verilog-to-routing / vtr-verilog-to-routing