added default filename generation for input flat placement file - Githubissues

verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

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added default filename generation for input flat placement file #2625

Closed KA7E closed 1 week ago

KA7E commented 1 week ago

Added code to construct a default flat placement input file name.

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[ ] Bug fix (change which fixes an issue)
[ ] New feature (change which adds functionality)
[ ] Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

[ ] My change requires a change to the documentation
[ ] I have updated the documentation accordingly
[ ] I have added tests to cover my changes
[ ] All new and existing tests passed