verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://verilogtorouting.org
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Remove `has_path_to_sink` #2626

Open amin1377 opened 1 week ago

amin1377 commented 1 week ago

This PR addresses the Issue #2611

vaughnbetz commented 2 days ago

Looks good; will merge after some QoR data has been checked and posted.