verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://verilogtorouting.org
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RR graph edge creation uses a incorrect switch type for decremental tracks #2630

Closed saaramahmoudi closed 2 days ago

saaramahmoudi commented 5 days ago

Description

While creating RR edge, incremental and decremental tracks use the same seg_details of inc_track. Although this is incorrect, it doesn't affect the quality of results because we don't have an architecture that uses different muxes for incremental and decremental tracks. So, I don't expect anything to change by this fix.

Types of changes

vaughnbetz commented 5 days ago

Thanks Sara. Will merge once CI is green, although as you say this looks quite safe.