verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://verilogtorouting.org
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VTR_LOG to print Fc values for pins bug #2631

Closed saaramahmoudi closed 3 days ago

saaramahmoudi commented 3 days ago

Description

After introducing the flat router, the function "block_type_pin_index_to_name" requires the third argument "is_flat". Since the function was called within ifdef, it was never fixed.

Types of changes