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Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://verilogtorouting.org
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Remove +1 from wirelength estimate #2655

Open amin1377 opened 1 month ago

amin1377 commented 1 month ago

To calculate the wirelength estimate or BB cost, we used the following formula: (bb.xmax - bb.xmin + 1) * crossing; We should try to get rid of the +1 in these and see if it cuts CPU time a little. It wouldn't affect optimization since it's a constant, although it would affect our wirelength estimates a little (but we could retune the wirelength estimates done after placement to correct for that).

vaughnbetz commented 1 month ago

Also lets us get rid of some min/max functions in the placement cost function if we make the inverse_channel_capacity matrix a bit bigger: I think 0 to width-1 and so on, instead of 1 to width - 2.