verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://verilogtorouting.org
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Turn on choke point analysis in the router by default, and make help etc. more user-friendly #2750

Open vaughnbetz opened 1 month ago

vaughnbetz commented 1 month ago

Many architectures need choke point analysis to be on to converge when flat routing is selected. Right now users have to turn this on themselves, which makes flat routing harder to use. We should turn this option on by default (only flat routing will be affected) and we should improve its help and add it to the command line documentation.

Proposed Behaviour

route_grp.add_argument(args.has_choking_spot, “–has_choking_spot”) Rename to –router_opt_choke_points New help: Some FPGA architectures with limited fan-out options within a cluster (e.g. fracturable LUTs with shared pins) do not converge well in routing unless these fan-out choke points are discovered and optimized for during net routing. This option helps router convergence for such architectures. Default: On (turns off for non-flat) (measure downside) Other values on / off.

Current Behaviour

Not on by default, and the name isn't great. Also not in the VTR documentation. It does have a CPU time hit: 11% total VTR time and 27% memory footprint on Titan to turn this on for the SIV architecture (which doesn't need it). But now the flagship architecture will route by default.

Possible Solution

Context

QuickLogic (and others) have found flat routing doesn't converge when they first run it. This will make it easier to use.

@duck2 @ganeshgore

fkosar-ql commented 1 month ago

Just checked with vtr_reg_strong and setting choke point analysis to true seems to fix all routing failures with the flat router

vaughnb-cerebras commented 1 month ago

Yaay! Amin is going to turn it on by default.