Empty Truth Table for Buffer/Passthrough LUT(s)

[breadgravy]

LUT(s) that are inserted into the physical netlist as passthroughs do not have truth tables in the atom netlist, nor do they have children LUTs.

Expected Behaviour

• pb blocks for LUTs should have a primitive child_pb "lut" created for them.
• All LUTs used to implement the netlist should have an associated atom block id and truth table.

Current Behaviour

• Passthrough LUTs do not have any block_id or truth table associated in the atom netlist.
• Passthrough LUT t_pb(s) do not have any primitive "lut" pb as children (child_pbs is NULL).

Possible Solution

When passthrough LUTs are created generate corresponding truth table entries in the atom netlist.

Steps to Reproduce (for bugs)

1. run VPR using following command (can use another debugger) testcase_files.zip

   gdb --args  ./vpr  arch/sIII_arch_med.xml ./temp/add2.pre-vpr.blif

2. Finish all routing and placement (_place_androute.cpp:372 is a good place to put a breakpoint)

3. The following gdb command should print the address of a pb lut6 that is missing a truth table. Note this is incredibly brittle way to replicate this; it may be better to just write some code to search for these cases.

   print  (g_vpr_ctx.clustering().clb_nlist.block_pb(  g_vpr_ctx.placement().grid_blocks[1][4].blocks[0] )) ->child_pbs[0][3]->child_pbs[0][0]->child_pbs[0][0]

testcase_files.zip

4. The child of the aforementioned block has type "lut6", but has no child_pb and has no associated truth table. The following code however shows that there is an atom net associated with one of the inputs to the LUT pb (where "pb" is the "lut6" physical block). This demonstrates the block is used, but does not have a truth table.

int p_pin_count = pb->pb_graph_node->input_pins[0][0].pin_count_in_cluster;
p_net = toplevel_pb->pb_route[p_pin_count].atom_net_id;

Context

This issue seems to be not so much a bug but an unstated convention, wherein extra LUTs used as routing are not inserted into the netlist . This affects generation of bitstreams from VTR/VPR as truth tables typically determine the configuration memory for LUTs. Reverse engineering the correct configuration for routing is messy if you do not have a truth table.

Your Environment

• VTR revision used: VTR 8.0
• Operating System and version: Linux (4.14.13-1-ARCH)
• Compiler version: g++ (7.2.1)

[kmurray]

Thanks for the detailed report.

Would it be possible to attach the architecture and netlist you used?

[breadgravy]

I updated the description with testcase files and a (hopefully) working method to replicate the problem.