System Verilog support is broken due to compilation error in F4PGA plugin

[MohamedElgammal]

The System Verilog support is broken as it requires enabling YOSYS_F4PGA_PLUGINS and doing so gets a compilation error as follows:

vtr-verilog-to-routing/libs/EXTERNAL/yosys-f4pga-plugins/systemverilog-plugin/third_party/yosys/simplify.cc:155:8: error: ‘struct Yosys::AST::AstNode’ has no member named ‘multirange_dimensions’ 155 | node->multirange_dimensions.push_back(rnode->range_right); | ^~~~~~~~~~~~~~~~~~~~~ .../vtr-verilog-to-routing/libs/EXTERNAL/yosys-f4pga-plugins/systemverilog-plugin/third_party/yosys/simplify.cc:156:8: error: ‘struct Yosys::AST::AstNode’ has no member named ‘multirange_dimensions’

[vaughnbetz]

@soheilshahrouz : in case you feel like a tour of some yosys + C++ stuff ...

[hzeller]

Isn't the systemverilog plugin called synlig for a while now ? I suspect this pulls in a somewhat old version...

[amirarjmand93]

I have been testing Synlig for integration, and so far it appears to be a suitable tool for SystemVerilog, rather than using it as just a standalone parser and elaborator, like Surlog. I will provide updates here along with some screenshots of my progress asap.

[amirarjmand93]

@vaughnbetz I executed some SystemVerilog designs of the VTR flow benchmark. It passed from Synlig, Parmys, Yosys, and VPR end-to-end successfully. It seems OK, but it takes more time to integrate fully. I am trying to solve it.

[vaughnbetz]

That's good news! Thanks @amirarjmand93.