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Verilog to Routing -- Open Source CAD Flow for FPGA Research
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VPRs warn that .input blocks should be swept. #324

Open mithro opened 6 years ago

mithro commented 6 years ago

Logging this bug as @kmurray asked.

Blocks which are .Input have no input pins. This causes VPR to warn with the following;

Complex block 0: O, type: BLK_TI-LUTFF .                                              
Complex block 1: out:O, type: BLK_IG-OBUF .                                            
Complex block 2: I0, type: BLK_IG-IBUF .                                               
Complex block 3: I1, type: BLK_IG-IBUF .                                                
Complex block 4: I2, type: BLK_IG-IBUF .                                               
Complex block 5: I3, type: BLK_IG-IBUF .                                                
        EMPTY: # blocks: 0, average # input + clock pins used: 0, average # output pins used: 0                                    
        BLK_IG-IBUF: # blocks: 4, average # input + clock pins used: 0, average # output pins used: 1                                                                                         
        BLK_IG-OBUF: # blocks: 1, average # input + clock pins used: 1, average # output pins used: 0
        BLK_TI-LUTFF: # blocks: 1, average # input + clock pins used: 4, average # output pins used: 1
Absorbed logical nets 0 out of 5 nets, 5 nets not absorbed.                           

Netlist conversion complete.                                                                                                               

Packing took 0.03 seconds                                                                                                                  
Load Packing                                                                                                                               
Begin loading packed FPGA netlist file.                                                                                                    
Netlist generated from file 'lut.net'.                                                                                                     
Finished loading packed FPGA netlist file (took 0.016114 seconds).                                                                         
Load Packing took 0.02 seconds                                                                                                             
Warning 6: Logic block #2 (I0) has only 1 input pin 'I0.I[0]' -- the whole block is hanging logic that should be swept.                    
Warning 7: Logic block #3 (I1) has only 1 input pin 'I1.I[0]' -- the whole block is hanging logic that should be swept.                    
Warning 8: Logic block #4 (I2) has only 1 input pin 'I2.I[0]' -- the whole block is hanging logic that should be swept.                    
Warning 9: Logic block #5 (I3) has only 1 input pin 'I3.I[0]' -- the whole block is hanging logic that should be swept.

Expected Behaviour

Input blocks are not warned about needing to be swept.

Steps to Reproduce (for bugs)

  1. Create an architecture where input blocks don't have any input pins.
  2. See vpr complain.

Your Environment

Seems to happen on both;

VPR FPGA Placement and Routing.                                                                                                                                                  
Version: 8.0.0-dev+vpr-7.0.5-5756-gcd10a5664-dirty                                     
Revision: vpr-7.0.5-5756-gcd10a5664-dirty                                              
Compiled: 2018-04-18T16:46:41 (debug build)                                                                                                                                                  
Compiler: GNU 6.3.0 on Linux-4.9.0-4-amd64 x86_64                                      
University of Toronto                                                                                                
vtr-users@googlegroups.com                                                             
This is free open source code under MIT license.
kmurray commented 6 years ago

This warning is a false positive.

This warning assumes that a block with no inputs is dead logic (since it isn't affected by anything else in the design).

Historically VPR used a single block type contained both .inputs and .outputs, which is why this warning didn't occur previously.

The fix is fairly straightforward:

  1. Identify the relevant code in vpr/src/base/check_netlist.cpp
  2. Guard it against firing for inputs with something like is_input_type() from vpr/src/uitl/vpr_utils.h.