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Verilog to Routing -- Open Source CAD Flow for FPGA Research
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No switch is specified for the ipin cblock #332

Closed mithro closed 6 years ago

mithro commented 6 years ago

Current Behaviour

Error 1: 
Type: Architecture file
File: /home/tansell/work/catx/vtr-verilog-to-routing/vpr/src/route/rr_graph.cpp
Line: 701
Message: No switch is specified for the ipin cblock, check if there is an error in arch file
Makefile:34: recipe for target 'wire.disp' failed

Steps to Reproduce (for bugs)

<?xml version="1.0"?>
<!-- set: ai sw=1 ts=1 sta et -->
<architecture xmlns:xi="http://www.w3.org/2001/XInclude">
  <models/>
  <layout>
    <fixed_layout height="2" name="JOHN" width="3">
      <single priority="1" type="MYIN"  x="0" y="0"/>
      <single priority="1" type="MYLUT" x="1" y="0"/>
      <single priority="1" type="MYOUT" x="2" y="0"/>
    </fixed_layout>
  </layout>
  <complexblocklist>
    <pb_type name="MYIN">
      <input name="DATIN" num_pins="2"/>
      <pb_type name="OUTPUT" blif_model=".output" num_pb="2">
        <input name="outpad" num_pins="1"/>
      </pb_type>
      <interconnect>
        <direct input="MYIN.DATIN[0]" name="O0" output="OUTPUT[0].outpad"/>
        <direct input="MYIN.DATIN[1]" name="O1" output="OUTPUT[1].outpad"/>
      </interconnect>
      <pinlocations pattern="custom">
        <loc side="right">MYIN.DATIN[0] MYIN.DATIN[1]</loc>
      </pinlocations>
      <fc in_type="frac" in_val="1.0" out_type="frac" out_val="1.0"/>
    </pb_type>

    <pb_type name="MYOUT">
      <output name="DATOUT" num_pins="1"/>
      <pb_type name="INPUT" blif_model=".input" num_pb="1">
        <output name="inpad" num_pins="1"/>
      </pb_type>
      <interconnect>
        <direct name="2" input="INPUT.inpad" output="MYOUT.DATOUT"/>
      </interconnect>
      <pinlocations pattern="custom">
        <loc side="left">MYOUT.DATOUT[0]</loc>
      </pinlocations>
      <fc in_type="frac" in_val="1.0" out_type="frac" out_val="1.0"/>
    </pb_type>

    <pb_type name="MYLUT">
      <input name="DATIN" num_pins="1"/>
      <output name="DATOUT" num_pins="1"/>
      <pb_type name="LUT" blif_model=".names" class="lut" num_pb="1">
        <input name="in" num_pins="1" port_class="lut_in"/>
    <output name="out" num_pins="1" port_class="lut_out"/>
    <delay_matrix in_port="LUT.in" out_port="LUT.out" type="max">10e-12</delay_matrix>
      </pb_type>
      <interconnect>
        <direct name="1" input="MYLUT.DATIN" output="LUT.in"/>
        <direct name="2" input="LUT.out" output="MYLUT.DATOUT"/>
      </interconnect>
      <pinlocations pattern="custom">
    <loc side="right">MYLUT.DATIN[0]</loc>
    <loc side="left">MYLUT.DATOUT[0]</loc>
      </pinlocations>
      <fc in_type="frac" in_val="1.0" out_type="frac" out_val="1.0"/>
    </pb_type>

  </complexblocklist>

  <device>
    <sizing R_minW_nmos="6065.520020" R_minW_pmos="18138.500000"/>
    <area grid_logic_tile_area="14813.392"/>
    <connection_block input_switch_name="my_switch"/>
    <switch_block fs="3" type="wilton"/>
    <chan_width_distr>
      <x distr="uniform" peak="1.000000"/>
      <y distr="uniform" peak="1.000000"/>
    </chan_width_distr>
  </device>

  <switchlist>
    <switch Cin="1233-12" Cout="123e-12" R="100" Tdel="1e-9" buf_size="23.54" mux_trans_size="2.32" name="my_switch" type="mux"/>
  </switchlist>
  <segmentlist>
    <segment Cmetal="22.5e-15" Rmetal="101" freq="1.0" length="1" name="L4" type="unidir">
      <sb type="pattern">1 1</sb>
      <cb type="pattern">1</cb>
      <mux name="my_switch"/>
      <wire_switch name="my_switch"/>
      <opin_switch name="my_switch"/>
    </segment>
  </segmentlist>
</architecture>
/home/tansell/work/catx/vtr-verilog-to-routing/vpr/vpr ../arch.xml --device JOHN --sweep_dangling_blocks off ../wire.blif --disp on

Using up to 1 parallel worker(s)

Architecture file: ../arch.xml
Circuit name: wire

Warning 1: Non-zero switch output capacitance (1.23e-10) has no effect when switch 'my_switch' is used for connection block inputs
Building complex block graph.
Load circuit
Load circuit took 0.00 seconds
Clean circuit
Absorbing 1 LUT buffers
Swept input(s) : 0
Swept output(s): 0 (0 dangling, 0 constant)
Swept net(s)   : 0
Swept block(s) : 0
Clean circuit took 0.00 seconds
Compress circuit
Compress circuit took 0.00 seconds
Verify circuit
Verify circuit took 0.00 seconds
Circuit Statistics:
  Blocks: 3
    .input :       1
    .output:       1
    1-LUT  :       1
  Nets  : 2
    Avg Fanout:     1.0
    Max Fanout:     1.0
    Min Fanout:     1.0
  Netlist Clocks: 0
Build Timing Graph
  Timing Graph Nodes: 4
  Timing Graph Edges: 3
Build Timing Graph took 0.00 seconds
Load Timing Constraints

SDC file 'wire.sdc' not found
Setting default timing constraints:
   * constrain all primay inputs and primary outputs on a virtual external clock 'virtual_io_clock'
   * optimize virtual clock to run as fast as possible
Timing constraints created 1 clocks
Netlist contains 0 clocks

Load Timing Constraints took 0.00 seconds
Timing analysis: ON
Slack definition: 
Circuit netlist file: wire.net
Circuit placement file: wire.place
Circuit routing file: wire.route
Circuit SDC file: wire.sdc

Packer: ENABLED
Placer: ENABLED
Router: ENABLED
Analysis: ENABLED

NetlistOpts.abosrb_buffer_luts            : true
NetlistOpts.sweep_dangling_primary_ios    : true
NetlistOpts.sweep_dangling_nets           : true
NetlistOpts.sweep_dangling_blocks         : false
NetlistOpts.sweep_constant_primary_outputs: false

PackerOpts.allow_unrelated_clustering: true
PackerOpts.alpha_clustering: 0.750000
PackerOpts.beta_clustering: 0.900000
PackerOpts.cluster_seed_type: TIMING
PackerOpts.connection_driven: true
PackerOpts.global_clocks: true
PackerOpts.hill_climbing_flag: false
PackerOpts.inter_cluster_net_delay: 1.000000
PackerOpts.timing_driven: true

PlacerOpts.place_freq: PLACE_ONCE
PlacerOpts.place_algorithm: PATH_TIMING_DRIVEN_PLACE
PlacerOpts.pad_loc_type: FREE
PlacerOpts.place_cost_exp: 1.000000
PlacerOpts.place_chan_width: 100
PlacerOpts.inner_loop_recompute_divider: 0
PlacerOpts.recompute_crit_iter: 1
PlacerOpts.timing_tradeoff: 0.500000
PlacerOpts.td_place_exp_first: 1.000000
PlacerOpts.td_place_exp_last: 8.000000
PlaceOpts.seed: 1
AnnealSched.type: AUTO_SCHED
AnnealSched.inner_num: 1.000000

RouterOpts.route_type: DETAILED
RouterOpts.router_algorithm: TIMING_DRIVEN
RouterOpts.base_cost_type: DELAY_NORMALIZED
RouterOpts.fixed_channel_width: NO_FIXED_CHANNEL_WIDTH
RouterOpts.trim_empty_chan: false
RouterOpts.trim_obs_chan: false
RouterOpts.acc_fac: 1.000000
RouterOpts.bb_factor: 3
RouterOpts.bend_cost: 0.000000
RouterOpts.first_iter_pres_fac: 0.000000
RouterOpts.initial_pres_fac: 0.500000
RouterOpts.pres_fac_mult: 1.300000
RouterOpts.max_router_iterations: 50
RouterOpts.min_incremental_reroute_fanout: 64
RouterOpts.astar_fac: 1.200000
RouterOpts.criticality_exp: 1.000000
RouterOpts.max_criticality: 0.990000
RouterOpts.routing_failure_predictor = SAFE
RouterOpts.routing_budgets_algorithm = DISABLE

AnalysisOpts.gen_post_synthesis_netlist: false

RoutingArch.directionality: UNI_DIRECTIONAL
RoutingArch.switch_block_type: WILTON
RoutingArch.Fs: 3

Packing
Begin packing '../wire.blif'.

After removing unused inputs...
    total blocks: 3, total nets: 2, total inputs: 1, total outputs: 1
Begin prepacking.
Finish prepacking.
Using inter-cluster delay: 4.56985e-07
Not enough resources expand FPGA size to (3 x 2)
Complex block 0: out:do, type: MYIN .
Complex block 1: do, type: MYLUT .
Complex block 2: di, type: MYOUT .
    EMPTY: # blocks: 0, average # input + clock pins used: 0, average # output pins used: 0
    MYIN: # blocks: 1, average # input + clock pins used: 1, average # output pins used: 0
    MYOUT: # blocks: 1, average # input + clock pins used: 0, average # output pins used: 1
    MYLUT: # blocks: 1, average # input + clock pins used: 1, average # output pins used: 1
Absorbed logical nets 0 out of 2 nets, 2 nets not absorbed.

Netlist conversion complete.

Packing took 0.03 seconds
Load Packing
Begin loading packed FPGA netlist file.
Netlist generated from file 'wire.net'.
Finished loading packed FPGA netlist file (took 0.015827 seconds).
Load Packing took 0.02 seconds
Warning 2: Logic block #2 (di) has only 1 input pin 'di.DATOUT[0]' -- the whole block is hanging logic that should be swept.

Netlist num_nets: 2
Netlist num_blocks: 3
Netlist EMPTY blocks: 0.
Netlist MYIN blocks: 1.
Netlist MYOUT blocks: 1.
Netlist MYLUT blocks: 1.
Netlist inputs pins: 1
Netlist output pins: 1

FPGA sized to 3 x 2 (JOHN)

Resource usage...
    Netlist      0  blocks of type: EMPTY
    Architecture 0  blocks of type: EMPTY
    Netlist      1  blocks of type: MYIN
    Architecture 1  blocks of type: MYIN
    Netlist      1  blocks of type: MYOUT
    Architecture 1  blocks of type: MYOUT
    Netlist      1  blocks of type: MYLUT
    Architecture 1  blocks of type: MYLUT

Device Utilization: 0.50 (target 1.00)
    Block Utilization: 0.00 Type: EMPTY
    Block Utilization: 1.00 Type: MYIN
    Block Utilization: 1.00 Type: MYOUT
    Block Utilization: 1.00 Type: MYLUT

Placement

Starting placement delay look-up...
Starting build routing resource graph...
Fc Actual Values: type = MYIN, pin = 0, seg = 0 (L4), Fc_out = 0, Fc_in = 8.
Fc Actual Values: type = MYIN, pin = 1, seg = 0 (L4), Fc_out = 0, Fc_in = 8.
Fc Actual Values: type = MYOUT, pin = 0, seg = 0 (L4), Fc_out = 8, Fc_in = 0.
Fc Actual Values: type = MYLUT, pin = 0, seg = 0 (L4), Fc_out = 0, Fc_in = 8.
Fc Actual Values: type = MYLUT, pin = 1, seg = 0 (L4), Fc_out = 8, Fc_in = 0.
Placement took 0.00 seconds
Error 1: 
Type: Architecture file
File: /home/tansell/work/catx/vtr-verilog-to-routing/vpr/src/route/rr_graph.cpp
Line: 701
Message: No switch is specified for the ipin cblock, check if there is an error in arch file
Makefile:34: recipe for target 'wire.disp' failed
make: *** [wire.disp] Error 1

Seems to be coming from;

    /* now we need to set the wire_to_rr_ipin_switch variable which points the detailed routing architecture
       to the representative ipin cblock switch. currently we're not allowing the specification of an ipin cblock switch
       with multiple fan-ins, so right now there's just one. May change in the future, in which case we'd need to 
       return a representative switch */
    if (switch_fanin[wire_to_arch_ipin_switch].count(UNDEFINED)) {
        /* only have one ipin cblock switch. OK. */
        (*wire_to_rr_ipin_switch) = switch_fanin[wire_to_arch_ipin_switch][UNDEFINED];
    } else if (switch_fanin[wire_to_arch_ipin_switch].size() != 0) {
        vpr_throw(VPR_ERROR_ARCH, __FILE__, __LINE__,
                "Not currently allowing an ipin cblock switch to have multiple fan-ins");
    } else {
        vpr_throw(VPR_ERROR_ARCH, __FILE__, __LINE__,
                "No switch is specified for the ipin cblock, check if there is an error in arch file");
    }

Your Environment

VPR FPGA Placement and Routing.
Version: 8.0.0-dev+vpr-7.0.5-5770-g5234d7d81
Revision: vpr-7.0.5-5770-g5234d7d81
Compiled: 2018-04-24T14:56:05 (release build)
Compiler: GNU 6.3.0 on Linux-4.9.0-5-amd64 x86_64
University of Toronto
vtr-users@googlegroups.com
This is free open source code under MIT license.
kmurray commented 6 years ago

So the root cause of this, is that the architecture as specified never produces any connection blocks.

With the original layout:

  <layout>
    <fixed_layout height="2" name="JOHN" width="3">
      <single priority="1" type="MYIN"  x="0" y="0"/>
      <single priority="1" type="MYLUT" x="1" y="0"/>
      <single priority="1" type="MYOUT" x="2" y="0"/>
    </fixed_layout>
  </layout>

The blocks are all at y=0 which puts them along the bottom edge (perimeter) of the device, causing them to have no vertical routing channels next to them: image Since the pins are assigned to the left/right sides they have no vertical channels to connect to, means no connection blocks are built (causing the error message).

A potential fix is changing the device grid so that the block pins are adjacent to routing channels by shifting them all up (y=1):

    <fixed_layout height="3" name="JOHN" width="3">
      <single priority="1" type="MYIN"  x="0" y="1"/>
      <single priority="1" type="MYLUT" x="1" y="1"/>
      <single priority="1" type="MYOUT" x="2" y="1"/>
    </fixed_layout>

which produces: image

Which will build and route successfully.

I will converted error to a warning and clarified the message. This allows the RR graph checker to run (which reports numerous issues with disconnected tracks etc.), and will allow users to see the RR graph in graphics. This extra information should help them understand why this is occurring.

For example, on the original architecture VPR would now produce:

Attempting to route at 2 channels (binary search bounds: [-1, -1])
Starting build routing resource graph...
Warning 4: No switch found for the ipin cblock in RR graph. Check if there is an error in arch file, or if no connection blocks are being built in RR graph
Warning 5: Track 0 had no switches
Warning 6: Track 1 had no switches
Warning 7: in check_rr_node: RR node: 10 type: CHANX location: (1,0) track: 0 len: 0 seg_type: L4 dir: INC_DIR has no out-going edges.
Warning 8: in check_rr_node: RR node: 11 type: CHANX location: (1,0) track: 1 len: 0 seg_type: L4 dir: DEC_DIR has no out-going edges.
Warning 9: in check_rr_graph: fringe node 2 IPIN at (0,0) has no fanin.
         This is possible on a fringe node based on low Fc_out, N, and certain lengths.
kmurray commented 6 years ago

Changes made in 0dc8802.

mithro commented 6 years ago

@kmurray In this case I guess we need to pad the Y=1 side of the architecture with empties so that we end up with segments in the space between the X=0 || X=1 and the X=1 || X=2.

mithro commented 6 years ago

This issue would also have been very obvious if I had seen it in the GUI. How were you able to get that graphic? (It that what the converting to warnings did?)

I think this shows maybe why we need to put some effort into https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/285

kmurray commented 6 years ago

Yes, the conversion to a warning allows things to continue to the GUI.