Closed mithro closed 6 years ago
So the root cause of this, is that the architecture as specified never produces any connection blocks.
With the original layout:
<layout>
<fixed_layout height="2" name="JOHN" width="3">
<single priority="1" type="MYIN" x="0" y="0"/>
<single priority="1" type="MYLUT" x="1" y="0"/>
<single priority="1" type="MYOUT" x="2" y="0"/>
</fixed_layout>
</layout>
The blocks are all at y=0
which puts them along the bottom edge (perimeter) of the device, causing them to have no vertical routing channels next to them:
Since the pins are assigned to the left/right sides they have no vertical channels to connect to, means no connection blocks are built (causing the error message).
A potential fix is changing the device grid so that the block pins are adjacent to routing channels by shifting them all up (y=1
):
<fixed_layout height="3" name="JOHN" width="3">
<single priority="1" type="MYIN" x="0" y="1"/>
<single priority="1" type="MYLUT" x="1" y="1"/>
<single priority="1" type="MYOUT" x="2" y="1"/>
</fixed_layout>
which produces:
Which will build and route successfully.
I will converted error to a warning and clarified the message. This allows the RR graph checker to run (which reports numerous issues with disconnected tracks etc.), and will allow users to see the RR graph in graphics. This extra information should help them understand why this is occurring.
For example, on the original architecture VPR would now produce:
Attempting to route at 2 channels (binary search bounds: [-1, -1])
Starting build routing resource graph...
Warning 4: No switch found for the ipin cblock in RR graph. Check if there is an error in arch file, or if no connection blocks are being built in RR graph
Warning 5: Track 0 had no switches
Warning 6: Track 1 had no switches
Warning 7: in check_rr_node: RR node: 10 type: CHANX location: (1,0) track: 0 len: 0 seg_type: L4 dir: INC_DIR has no out-going edges.
Warning 8: in check_rr_node: RR node: 11 type: CHANX location: (1,0) track: 1 len: 0 seg_type: L4 dir: DEC_DIR has no out-going edges.
Warning 9: in check_rr_graph: fringe node 2 IPIN at (0,0) has no fanin.
This is possible on a fringe node based on low Fc_out, N, and certain lengths.
Changes made in 0dc8802.
@kmurray In this case I guess we need to pad the Y=1 side of the architecture with empties so that we end up with segments in the space between the X=0 || X=1
and the X=1 || X=2
.
This issue would also have been very obvious if I had seen it in the GUI. How were you able to get that graphic? (It that what the converting to warnings did?)
I think this shows maybe why we need to put some effort into https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/285
Yes, the conversion to a warning allows things to continue to the GUI.
Current Behaviour
Steps to Reproduce (for bugs)
Seems to be coming from;
Your Environment