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Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://verilogtorouting.org
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Make the placement move generator explore sparse blocks / heterogeneous floorplans more systematically #423

Open vaughnbetz opened 5 years ago

vaughnbetz commented 5 years ago

Proposed Behaviour

The placement move generator can probably be improved (see src/place.c, find_to_location). It should search nearby blocks of the proper type, with the range limit interpreted as how many block locations of that type it can search over.

Current Behaviour

Sufficiently common blocks will be searched as above (using the placement grid). Less common ones will be swapped randomly (one if case) or could be locked down early due to the range limit.

Possible Solution

Could search blocks in their own, custom grid space respecting the range limit within that space, and then map back to the full grid.

Context

May be impacting placement quality on heterogenous devices.

vaughnbetz commented 5 years ago

Also should look at macro placement move generation to make sure they don't get locked down early or move too infrequently.