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Verilog to Routing -- Open Source CAD Flow for FPGA Research
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PVT corner timing models #551

Open litghost opened 5 years ago

litghost commented 5 years ago

Proposed Behaviour

Timing models are generally preformed at a particular process, voltage and temperature (PVT) corner. VTR currently only supports one process corner. Using a slow process corner is likely sufficient if slack timing is the dominate issue during routing, but in fast corners, I believe hold timing violations become possible.

Enabling multiple versions of timing models (at a minimum a fast and slow model) would enable corner analysis and optimization on designs that require that fidelity.

Current Behaviour

A single process corner is supported.

Possible Solution

Context

7-series timing models have both SLOW (slow process, low voltage, high temp) and FAST corners (fast process, high voltage, low temp). Other parts may have additional PVT corner models as well. Analysis of multiple corners is possible on a routed design, but PnR optimization can at most be run at one corner.

litghost commented 5 years ago

This is likely a low priority change, but something to think about putting on the road map.

kmurray commented 5 years ago

Agreed, this is a good thing to put on the roadmap.

One item I know has been discussed is better encapsulation of the device delay model. At the moment the delay model is spread through-out the code base, some in the PB type hierarchy and some in the RR graph. To support this it probably makes sense to factor the delay model out of those components and into a separate encapsulated data structure (which can be easily swapped for a different PVT, or multiple PVTs supported).

kmurray commented 5 years ago

Another note, is that Tatum (VTR's STA library) can be extended to perform simultaneous PVT analysis efficiently (via SIMD). That code never made it back into master, but is something to re-consider at the point where fast multi-PVT analysis is required (i.e. during optimization).

sharmaln commented 3 years ago

From eFPGA fabric perspective, it is important to do STA on different process corners. I am wondering if this issue is still in lower priority or are you planning to address this in near future? We are currently using VTR for our new QuickLogic eFPGA devices and this feature is really helpful for our users.