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Reading symbols from ./odin_II...done.
(gdb) r
Starting program: /home/jbrown17/workspace/vtr-verilog-to-routing/ODIN_II/odin_II -V regression_test/benchmark/my_bugs/matmul.v
[Thread debugging using libthread_db enabled]
Using host libthread_db library "/usr/lib/libthread_db.so.1".
--------------------------------------------------------------------
Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)
Email: jamieson.peter@gmail.com and ken@unb.ca for support issues
--------------------------------------------------------------------
High-level synthesis Begin
Parser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)
Preprocessing verilog.
Optimizing module by AST based optimizations
Converting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)
--------------
Odin has decided you MAY fail ... :
WARNING (1):NETLIST_ERROR Rounding memory <matrixA> of size <15> to closest power of two: 16.
WARNING (2):NETLIST_ERROR Rounding memory <matrixB> of size <15> to closest power of two: 16.
WARNING (3):NETLIST_ERROR Rounding memory <tmp1> of size <15> to closest power of two: 16.
WARNING (4):NETLIST_ERROR Rounding memory <tmp2> of size <15> to closest power of two: 16.
WARNING (5):NETLIST_ERROR Rounding memory <tmp3> of size <15> to closest power of two: 16.
WARNING (6):NETLIST_ERROR Rounding memory <tmp4> of size <15> to closest power of two: 16.
WARNING (7):NETLIST_ERROR Rounding memory <tmp5> of size <15> to closest power of two: 16.
WARNING (8):NETLIST_ERROR Rounding memory <tmp6> of size <15> to closest power of two: 16.
WARNING (9):NETLIST_ERROR Rounding memory <tmp7> of size <15> to closest power of two: 16.
Program received signal SIGSEGV, Segmentation fault.
convert_multi_to_single_dimentional_array (node=0x5555558a46e0) at /home/jbrown17/workspace/vtr-verilog-to-routing/ODIN_II/SRC/netlist_create_from_ast.cpp:5976
5976 array_row = local_symbol_table[sc_spot]->types.variable.initial_value;
(gdb) bt
#0 convert_multi_to_single_dimentional_array (node=0x5555558a46e0) at /home/jbrown17/workspace/vtr-verilog-to-routing/ODIN_II/SRC/netlist_create_from_ast.cpp:5976
#1 0x0000555555702fa6 in assignment_alias (assignment=0x5555558a4a20, instance_name_prefix=0x7fffffffddc4 "top") at /home/jbrown17/workspace/vtr-verilog-to-routing/ODIN_II/SRC/netlist_create_from_ast.cpp:3273
#2 0x00005555556fa38c in netlist_expand_ast_of_module (node=0x5555558a4a20, instance_name_prefix=0x7fffffffddc4 "top") at /home/jbrown17/workspace/vtr-verilog-to-routing/ODIN_II/SRC/netlist_create_from_ast.cpp:815
#3 0x00005555556fa4d6 in netlist_expand_ast_of_module (node=0x5555558a38c0, instance_name_prefix=0x7fffffffddc4 "top") at /home/jbrown17/workspace/vtr-verilog-to-routing/ODIN_II/SRC/netlist_create_from_ast.cpp:855
#4 0x000055555570682d in create_if_mux_statements (if_ast=0x5555558a5a80, if_node=0x555555977ae0, instance_name_prefix=0x7fffffffddc4 "top") at /home/jbrown17/workspace/vtr-verilog-to-routing/ODIN_II/SRC/netlist_create_from_ast.cpp:4433
#5 0x00005555557065a0 in create_if (if_ast=0x5555558a5a80, instance_name_prefix=0x7fffffffddc4 "top") at /home/jbrown17/workspace/vtr-verilog-to-routing/ODIN_II/SRC/netlist_create_from_ast.cpp:4348
#6 0x00005555556fa3ff in netlist_expand_ast_of_module (node=0x5555558a5a80, instance_name_prefix=0x7fffffffddc4 "top") at /home/jbrown17/workspace/vtr-verilog-to-routing/ODIN_II/SRC/netlist_create_from_ast.cpp:829
#7 0x00005555556fa4d6 in netlist_expand_ast_of_module (node=0x5555558a5b80, instance_name_prefix=0x7fffffffddc4 "top") at /home/jbrown17/workspace/vtr-verilog-to-routing/ODIN_II/SRC/netlist_create_from_ast.cpp:855
#8 0x00005555556fa4d6 in netlist_expand_ast_of_module (node=0x5555558a5c80, instance_name_prefix=0x7fffffffddc4 "top") at /home/jbrown17/workspace/vtr-verilog-to-routing/ODIN_II/SRC/netlist_create_from_ast.cpp:855
#9 0x00005555556fa4d6 in netlist_expand_ast_of_module (node=0x5555558932b0, instance_name_prefix=0x7fffffffddc4 "top") at /home/jbrown17/workspace/vtr-verilog-to-routing/ODIN_II/SRC/netlist_create_from_ast.cpp:855
#10 0x00005555556fa4d6 in netlist_expand_ast_of_module (node=0x5555558b9ce0, instance_name_prefix=0x7fffffffddc4 "top") at /home/jbrown17/workspace/vtr-verilog-to-routing/ODIN_II/SRC/netlist_create_from_ast.cpp:855
#11 0x00005555556f9e0c in convert_ast_to_netlist_recursing_via_modules (current_module=0x5555558b9ce0, instance_name=0x7fffffffddc4 "top", level=0)
at /home/jbrown17/workspace/vtr-verilog-to-routing/ODIN_II/SRC/netlist_create_from_ast.cpp:613
#12 0x00005555556f9187 in create_netlist () at /home/jbrown17/workspace/vtr-verilog-to-routing/ODIN_II/SRC/netlist_create_from_ast.cpp:394
#13 0x0000555555654a4e in synthesize_verilog () at /home/jbrown17/workspace/vtr-verilog-to-routing/ODIN_II/SRC/odin_ii.cpp:125
#14 0x0000555555654ddf in start_odin_ii (argc=3, argv=0x7fffffffe058) at /home/jbrown17/workspace/vtr-verilog-to-routing/ODIN_II/SRC/odin_ii.cpp:254
#15 0x00005555556545bb in main ()
(gdb) fr 0
#0 convert_multi_to_single_dimentional_array (node=0x5555558a46e0) at /home/jbrown17/workspace/vtr-verilog-to-routing/ODIN_II/SRC/netlist_create_from_ast.cpp:5976
5976 array_row = local_symbol_table[sc_spot]->types.variable.initial_value;
(gdb) print local_symbol_table
$1 = (ast_node_t **) 0x555555971c10
(gdb) print local_symbol_table[sc_spot]
$2 = (ast_node_t *) 0xc1
(gdb) print local_symbol_table[sc_spot]->types
Cannot access memory at address 0xd9
(gdb) print sc_spot
$3 = -1
(gdb) print sc_spot
$4 = -1
(gdb)
Current Behaviour
segfault when accessing 2d arrays in local param table
Possible Solution
check sc_spot is not negative
Steps to Reproduce
see bellow
Context
tried to compile the matmul.v file but 2d arrays seems to segfault due to sc_spot being negative in odin. would probably need a check
uname -a
gcc -v
matmul.v
gdb --args ./odin_II -V regression_test/benchmark/my_bugs/matmul.v