Odin Verilog support

[MohamedElgammal]

There are many unsupported constructs in Verilog that I faced while trying to run a verilog design through Odin. I have created a micro testcase for each of them and they can be found at: https://github.com/MohamedElgammal/Odin-issues

Steps to Reproduce

1. clone the repo
2. cd into any issue directory, you will find a readme that explains the issue and a micro design to reproduce it
3. run odin with the attached config file

Context

It errors out in some syntax that is supported in verilog LRM.

Your Environment

• VTR revision used:
• Operating System and version:
• Compiler version:

[jeanlego]

Thanks for this!

We are actively refactoring a lot of core components of Odin and we can definitely use more micro-test cases! Would you be ok with us including those in our regression suite?

[MohamedElgammal]

Sure you can.

[jeanlego]

Thank you! We will raise these as individual issue and reference this issue so you can track the development.

[jeanlego]

@msohrabi2019 can you verify that the issues are still there? And if so please raise new issue for each missing keyword or feature with a new verilog file to exercise the missing feature.

When creating the issue please refer to this issue so that it is easier to track. @MohamedElgammal was kind enough to let us use his verilog files, so you could inspire yourself from these for yours.

Thanks again @MohamedElgammal

[jeanlego]

@Shreyv could you have a look at the issues referenced? #977 is one of the thing you are currently working on

[Shreyv]

@jeanlego sure

[jeanlego]

@djns99 there are other linked issue here that you can start looking at @Shreyv can you create new issues from the linked verilog file from the OP. once done, can you start working through them.

@djns99 and @Shreyv the workflow should look like:

• Create a branch on https://github.com/CAS-Atlantic/vtr-verilog-to-routing (you should have rights to it)
• add the failing benchmark,
• update Odin QoR to reflect failing benchmark
• add, commit and push the failing verilog files and the Odin QoR changes relevant to the issue
• make a WIP PR on this repo from the branch
• start work on the said issue.

@sdamghan can you do the first review on @djns99 and @Shreyv PR's once they submit them. Also @sdamghan can you have a look at the benchmark suite? Some new change now displays known to fail benchmark that should pass as part of Verilog 2005, could you please create issues for benchmarks that show failing but are expected to pass, once done you can work on these issues alongside of @djns99 and @Shreyv.

[Shreyv]

@jeanlego Sure I will work on it

[sdamghan]

@jeanlego Sure, I'll handle it!