Odin should not need to check the order of ports that are instantiated by name when instantiating a module
Current Behaviour
Odin fails with a netlist error because the ports are out of order
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Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)
Email: jamieson.peter@gmail.com and ken@unb.ca for support issues
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High-level synthesis Begin
Parser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)
Adding file ../../../Odin-issues/port_order/top.v to parse list
Optimizing module by AST based optimizations
Converting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)
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Detected Top Level Module: top
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Odin has decided you have failed ;)
ERROR (1)::NETLIST_ERROR ../../../Odin-issues/port_order/top.v::4 This module entry does not match up correctly (in2 != out). Odin expects the order of ports to be the same
output out;
Assertion failed()@[/home/jbrown17/workspace/vtr-verilog-to-routing/ODIN_II/SRC/netlist_create_from_ast.cpp]connect_module_instantiation_and_alias::2328
[1] 7735 abort (core dumped) ./odin_II -V ../../../Odin-issues/port_order/top.v
Possible Solution
No need to check port order if the ports have been instantiated by name
Related Issue #848
Expected Behaviour
Odin should not need to check the order of ports that are instantiated by name when instantiating a module
Current Behaviour
Odin fails with a netlist error because the ports are out of order
Possible Solution
No need to check port order if the ports have been instantiated by name
Steps to Reproduce
Run Odin II with the verilog code provided by @MohamedElgammal top.v.txt Original Repo: https://github.com/MohamedElgammal/Odin-issues/tree/master/port_order
Your Environment
uname -a
gcc -v