Should be able to connect output port to vector element.
If this is not possible, Odin II should at least provide a meaningful error or warning message to help the developer to debug their code.
Current Behaviour
Odin II exits with a segfault, with no meaningful error or warning message
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Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)
Email: jamieson.peter@gmail.com and ken@unb.ca for support issues
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High-level synthesis Begin
Parser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)
Adding file ../../../Odin-issues/seg_fault/top.v to parse list
[1] 8722 segmentation fault (core dumped) ./odin_II -V ../../../Odin-issues/seg_fault/top.v
--------------------------------------------------------------------
Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)
Email: jamieson.peter@gmail.com and ken@unb.ca for support issues
--------------------------------------------------------------------
High-level synthesis Begin
Parser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)
Adding file ../../../Odin-issues/seg_fault/top.v to parse list
Optimizing module by AST based optimizations
Converting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)
==========================
Detected Top Level Module: and2
==========================
Performing Optimizations of the Netlist
Performing Partial Map to target device
Outputting the netlist to the specified output format
Successful High-level synthesis by Odin
Blif file available at default_out.blif
Ran in 1.3ms
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Odin ran with exit status: 0
Odin II took 0.00 seconds (max_rss 4.5 MiB)
Your Environment
uname -a
Linux JBpc 5.2.9-arch1-1-ARCH #1 SMP PREEMPT Fri Aug 16 11:29:43 UTC 2019 x86_64 GNU/Linux
Related Issue #848
Expected Behaviour
Should be able to connect output port to vector element. If this is not possible, Odin II should at least provide a meaningful error or warning message to help the developer to debug their code.
Current Behaviour
Odin II exits with a segfault, with no meaningful error or warning message
Steps to Reproduce
Run Odin II with the verilog file provided by @MohamedElgammal top.v.txt Original Repo: https://github.com/MohamedElgammal/Odin-issues/tree/master/seg_fault
Workaround
wire temp1; wire temp2; assign out[0] = temp1; assign out[1] = temp2;
and(temp1, in1[0],in2[0]); and(temp2, in1[1],in2[1]);
Your Environment
uname -a
gcc -v