Port list is not aligned properly when the first port declaration is not start from a new line

[veripoolbot]

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Author Name: Enzo Chi Original Redmine Issue: 1167 from https://www.veripool.org

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Found a issue of align the port list: (verilog-auto-lineup 'all)

When the first port declaration right after "(" as example below, the port name is not aligned correctly.

Port "sel" and the rest are not aligned.

module indent_case(input bit [1:0] sel,
                    input byte  a,
                    input byte  b,
                    input byte  c,
                    input byte  d,
                    output byte dout
                    );

Expect to be

module indent_case(input bit [1:0] sel,
                    input byte      a,
                    input byte      b,
                    input byte      c,
                    input byte      d,
                    output byte     dout
                    );

If "sel" declaration start from a new line, it works

module indent_case(
                    input bit [1:0] sel,
                    input byte      a,
                    input byte      b,
                    input byte      c,
                    input byte      d,
                    output byte     dout
                    );

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2017-11-19T13:38:15Z

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AFAIK still a problem, perhaps someone would like to contribute a patch?