Closed veripoolbot closed 2 years ago
Author Name: Enzo Chi Original Redmine Issue: 1167 from https://www.veripool.org
Found a issue of align the port list: (verilog-auto-lineup 'all)
When the first port declaration right after "(" as example below, the port name is not aligned correctly.
Port "sel" and the rest are not aligned.
module indent_case(input bit [1:0] sel, input byte a, input byte b, input byte c, input byte d, output byte dout );
Expect to be
If "sel" declaration start from a new line, it works
module indent_case( input bit [1:0] sel, input byte a, input byte b, input byte c, input byte d, output byte dout );
Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2017-11-19T13:38:15Z
AFAIK still a problem, perhaps someone would like to contribute a patch?
Author Name: Enzo Chi Original Redmine Issue: 1167 from https://www.veripool.org
Found a issue of align the port list: (verilog-auto-lineup 'all)
When the first port declaration right after "(" as example below, the port name is not aligned correctly.
Port "sel" and the rest are not aligned.
Expect to be
If "sel" declaration start from a new line, it works