search

veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
253 stars 90 forks source link

Is it possible to make "begin" keyword align with case expression? #1168

Open veripoolbot opened 7 years ago

veripoolbot commented 7 years ago

Author Name: Enzo Chi Original Redmine Issue: 1168 from https://www.veripool.org

We have coding style required the "begin" keyword has to align with the case expression:

Expected:

      case(sel)
          0:
          begin
              dout <= a;
          end

          ....
       endcase

But the verilog-mode always indent the "begin" as below:

      case(sel)
          0:
              begin
                  dout <= a;
              end

          ....
       endcase
veripoolbot commented 6 years ago

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2017-11-19T13:44:35Z

I don't believe there is presently a setting for this.

Note the indentation code is mostly maintained/improved as patches are contributed. So, perhaps you would like to consider contributing a patch for this?