AUTOINST with user defined type with a range

[veripoolbot]

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Author Name: Sergio Schuler (@schuler1) Original Redmine Issue: 1306 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)

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For the attached files, the regular expression doesn't seem to be filtering out the user defined type from AUTOINST Not sure if I am doing something wrong.

[veripoolbot]

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Original Redmine Comment Author Name: Sergio Schuler (@schuler1) Original Date: 2018-04-27T01:16:34Z

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Perhaps it is more helpful to search if the code appears in the bug's description

File: block_pkg.sv

package block_pkg;

    typedef struct packed {
       logic a;
       logic b;
    } sometype_t;

endpackage: block_pkg

// Local Variables:
// verilog-typedef-regexp: "_t \\[1:0\\]$"
// End:

File: block.sv

module block
  import block_pkg::*;
    (input clock,
     output sometype_t [1:0] someidentifier,

    assign someidentifier[1] = '0;
    assign someidentifier[0] = '0;

endmodule // block

// Local Variables:
// verilog-typedef-regexp: "_t \\[1:0\\]$"
// End:

File: top.sv

module top
  import block_pkg::*;
    ();

    wire clock;
    sometype_t [1:0] someidentifier;

    block
      block0(/*AUTOINST*/
             // Outputs
             .sometype_t                 (sometype_t/*.[1:0]*/),
             .someidentifier             (someidentifier),
             // Inputs
             .clock                      (clock));

endmodule // top

// Local Variables:
// verilog-typedef-regexp: "_t \\[1:0\\]$"
// End:

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2018-04-29T22:10:36Z

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verilog-typedef-regexp doesn't need the array. Use

// Local Variables:
// verilog-typedef-regexp: "_t$" 
// End:

[veripoolbot]

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Original Redmine Comment Author Name: Sergio Schuler (@schuler1) Original Date: 2018-04-30T02:06:03Z

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I tried what you suggested first, but unfortunately it doesn't work. I can provide an example if you need one.

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2018-04-30T07:39:11Z

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Your first example worked (I think) - if you have another that doesn't please attach or post it.

[veripoolbot]

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Original Redmine Comment Author Name: Sergio Schuler (@schuler1) Original Date: 2018-04-30T22:56:08Z

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My apologies. There was a configuration error that prevented evaluating verilog-typedef-regexp embedded in files. You are correct in saying this is not a bug.