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veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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Declaration prefixed with rand keyword is not prettified. #1335

Closed veripoolbot closed 5 years ago

veripoolbot commented 6 years ago

Author Name: Chan Gyu Lee Original Redmine Issue: 1335 from https://www.veripool.org

When doing lineup or prettifying code, declarations prefixed with rand keyword are ignored. I suggested "pull request":https://github.com/veripool/verilog-mode/pull/16 in github to handle this problem, and was instructed to create issue here.

Tests fail because as noted above, declarations with rand keyword are not originally being prettified. When I accordingly modified few test cases that contain such declarations, every other test cases passed without problem.

Are there any specific reasons for not prettifying rand property declarations?

veripoolbot commented 6 years ago

Original Redmine Comment Author Name: Alex Reed Original Date: 2018-08-28T13:52:10Z

There's no reason that I know of to exclude 'rand' from prettifying operations. I think this was just oversight. I'll patch the two tests that fail and promote this patch sometime later today hopefully.

veripoolbot commented 6 years ago

Original Redmine Comment Author Name: Chan Gyu Lee Original Date: 2018-09-07T04:39:40Z

I just noticed that there is another keyword 'randc' which also need to be added.

veripoolbot commented 5 years ago

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2018-11-29T19:48:24Z

Believe this was committed on Sep 4th.