veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
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A bug when a module's port is 2-dimension array #1357

Closed veripoolbot closed 6 years ago

veripoolbot commented 6 years ago

Author Name: Jin Xie Original Redmine Issue: 1357 from https://www.veripool.org


The example is, module test ( ... input [8-1:0] config_2d [3:0], ... );

when instantiating this module, the port config_2d will be connected as: .config_2d (config_2d[7:0]),

It is not expected.

veripoolbot commented 6 years ago

Original Redmine Comment Author Name: Jin Xie Original Date: 2018-09-30T09:25:19Z


The example is,

module test 
( 
... 
input [8-1:0] config_2d [3:0], 
... );
</code>

when instantiating this module using AUTO_TEMPLATE,

/* test AUTO_TEMPLATE (
    .\(.*\)   (xxx_\1[]),
)
*/
</code>

the port config_2d will be connected as:

 .config_2d (xxx_config_2d[7:0]),

</code>

It is not expected.

veripoolbot commented 6 years ago

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2018-09-30T09:42:10Z


By using .(.*) (xxx_\1[]),

you are asking for a 1D array connection. Use

.\(.*\)   (xxx_\1[][]),

It will then assume the 2D connection

           .config_2d                (xxx_config_2d/*[8-1:0].[3:0]*/));

The indices will be commented out as the assumption is a one-to-one connection, but an AUTOWIRE will create the 2D signal.