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Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
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AUTOREGINPUT does work if signal is on LHS of assign statement #1401

Closed veripoolbot closed 5 years ago

veripoolbot commented 5 years ago

Author Name: David Rogoff Original Redmine Issue: 1401 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)

Hi.

I have a wrapper module I'm working on. It instantiates a submodule that's all AUTOINST and I've got AUTOLOGIC, AUTOWIRE, and AUTOREGINPUT. The input port signals for the submodule should appear in the AUTOREGINPUT section. And they do - unless those signals appear in assign statements I have to rename wrapper ports (too complicated renaming to use AUTOINST template). I need to comment-out all the assigns, update AUTOS, and then un-comment-out the assigns. Is there a better way to do this?

Thanks,

David

veripoolbot commented 5 years ago

Original Redmine Comment Author Name: David Rogoff Original Date: 2019-02-26T18:36:18Z

Subject should be "does not work".

veripoolbot commented 5 years ago

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-02-26T22:24:09Z

In Verilog, it's illegal to have an "assign" targeting a "reg", so I presume you're using system Verilog? Could you use "wire foo = bar" instead of assign?

If not I assume you're asking for an e.g. verilog-auto-reg-input-ignore-assign you set to "t"?

veripoolbot commented 5 years ago

Original Redmine Comment Author Name: David Rogoff Original Date: 2019-02-27T18:08:08Z

Wilson Snyder wrote:

In Verilog, it's illegal to have an "assign" targeting a "reg", so I presume you're using system Verilog?

Correct

Could you use "wire foo = bar" instead of assign?

No, because the signals are output ports of the wrapper module, not internal signals

If not I assume you're asking for an e.g. verilog-auto-reg-input-ignore-assign you set to "t"?

I think so.

veripoolbot commented 5 years ago

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-03-08T02:21:10Z

Added new verilog-auto-reg-input-assigned-ignore-regexp to verilog-mode-2019-03-07-4cfa499-vpo.

You'd use it like this at the bottom of your file for your case:

// Local Variables:
// verilog-auto-reg-input-assigned-ignore-regexp: ".*"
// End: