alignment within generate-if

[veripoolbot]

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Author Name: Warren Ferguson Original Redmine Issue: 1404 from https://www.veripool.org

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I entered the following file and allowed verilog mode (latest verilog-mode.el) to choose its own alignment. Why is the first generate-if using always_comb choosing the unusual alignment of the else block, whereas the generate-if using assigns has the expected alignment?

module test
  #(paramweter integer OPT = 1
     )
    (input logic y,z;
    );

    if (OPT = 1) begin
       always_comb begin
          y = 1'b1;
       end
end else begin
    always_comb begin
       y = 1'b0;
    end
end

    if (OPT = 1) begin
       assign z = 1'b1;
    end else begin
       assign z = 1'b0;
    end

endmodule // test

[veripoolbot]

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Original Redmine Comment Author Name: Warren Ferguson Original Date: 2019-02-27T21:38:50Z

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Attached source file given that code in text was not interpreted correctly.

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-03-03T00:55:25Z

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Verilog-mode seems to mis-assume always_comb is left-most inside a module.

There might be a wait, generally indentation fixes will need to wait for someone to provide a patch.