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Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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Question: How can I use AUTOs to add the input/output attribution info. like "i_/o_" or "_i/_o" to the wires? #1417

Closed veripoolbot closed 5 years ago

veripoolbot commented 5 years ago

Author Name: Chen Jay Original Redmine Message: 2964 from https://www.veripool.org

I want to use AUTOs to add the input/output attribution info. like "i/o" or "_i/_o" to the connection wires, like:

inst inst (/* AUTOINST*
         //Outputs
         .lower_out (o_lower_out),
         //Inputs
         . lower_inb(i_lower_inb),
         . lower_ina (i_lower_ina));

or:

inst inst (/* AUTOINST*
         //Outputs
         .lower_out (lower_out_o),
         //Inputs
         . lower_inb(lower_inb_i),
         . lower_ina (lower_ina_i));

but do not know how to realize it, could you help on this.

veripoolbot commented 5 years ago

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-05-13T12:27:25Z

Use something like this:

  /* inst AUTO_TEMPLATE (
    .\(.*\) (@"(if (equal vl-dir \\"output\\") \\"o_\\" \\"i_\\")"\1),
    );
    */

That is for every signal, look at direction and if an output add o otherwise i, followed by original signal name.

veripoolbot commented 5 years ago

Original Redmine Comment Author Name: Chen Jay Original Date: 2019-05-14T00:34:01Z

Thanks for your kindly help！！！！！！！！

Best Regards， Chen Jay

veripoolbot commented 5 years ago

Original Redmine Comment Author Name: Chen Jay Original Date: 2019-05-15T01:19:01Z

Just for memo：

Add input/output/inout info. like "i/o/io_" to the wires:

.\(.*\) (@"(if (equal vl-dir \\"output\\") \\"o_\\" (if (equal vl-dir \\"input\\") \\"i_\\" \\"io_\\"))"\1[]),