Closed veripoolbot closed 5 years ago
Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-05-13T12:27:25Z
Use something like this:
/* inst AUTO_TEMPLATE (
.\(.*\) (@"(if (equal vl-dir \\"output\\") \\"o_\\" \\"i_\\")"\1),
);
*/
That is for every signal, look at direction and if an output add o otherwise i, followed by original signal name.
Original Redmine Comment Author Name: Chen Jay Original Date: 2019-05-14T00:34:01Z
Thanks for your kindly help!!!!!!!!
Best Regards, Chen Jay
Original Redmine Comment Author Name: Chen Jay Original Date: 2019-05-15T01:19:01Z
Just for memo:
Add input/output/inout info. like "i/o/io_" to the wires:
.\(.*\) (@"(if (equal vl-dir \\"output\\") \\"o_\\" (if (equal vl-dir \\"input\\") \\"i_\\" \\"io_\\"))"\1[]),
Author Name: Chen Jay Original Redmine Message: 2964 from https://www.veripool.org
I want to use AUTOs to add the input/output attribution info. like "i/o" or "_i/_o" to the connection wires, like:
or:
but do not know how to realize it, could you help on this.