Closed veripoolbot closed 5 years ago
Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-05-28T11:03:32Z
For now move the ifndef inside the #( that is:
#(
`ifndef SYNTHESIS
.FILENAME (`CPU_ROMFILE)
`endif
)
Verilog-mode has limited tolerance for ifdefs, but this case should have worked, I'll see if this can be easily fixed.
Original Redmine Comment Author Name: Ray Stevens Original Date: 2019-05-28T14:13:18Z
Thanks for the workaround! (and the very fast response).
Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-05-28T23:47:00Z
I don't see an obvious real fix, generally verilog-mode ignores most ifdefs and the parsing to handle this otherwise is leading to a mess, so we'll stick with the workaround as how it has to work...
Original Redmine Comment Author Name: Ray Stevens Original Date: 2019-05-29T00:38:52Z
OK, thanks for looking into this.
Author Name: Ray Stevens Original Redmine Issue: 1448 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
Hi Mac,
I was using this version of verilog-mode: You are using verilog-mode 2019-05-06-28bee25-vpo
To reproduce the issue, recompute AUTOs on attached ip0301 file. You should see this error message: Updating AUTOs... or: ip0301_cpuSubsystem.sv:209: Can’t locate ‘`endif’ module definition (Expanded macro to endif) Check the verilog-library-directories variable. I looked in (if not listed, doesn’t exist): /home/rstevens/elisp/bugs/embeddedIfndef/ip0301_cpuSubsystem.sv
If you search for "///" you will find two lines that you can comment out to get AUTOs to recompute successfully.
I included 2 lower level files that you will need to successfully recompute AUTOs.
Thanks, Ray Stevens