veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
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AUTOINOUTMODULE not working in emacs batch mode #1450

Closed veripoolbot closed 5 years ago

veripoolbot commented 5 years ago

Author Name: Sumit Singh Original Redmine Issue: 1450 from https://www.veripool.org


I am trying to generate shell files for given verilog modules. While doing this, I am encountering an issue when I try to use batch mode command for emacs.

Please find below more details;

When trying to generate shell files, I use following sample setup :

————————————————————- module example_shell (/AUTOARG/) /AUTOINOUTMODULE(“example”)/ endmodule

// Local Variables: // verilog-library-directories : (“.” “../common”) // verilog-library-files : (“../lib.sv” // End: ————————————————————

The main module definition exists in verilog file in same hierarchy and with local variables we are able to get the information. This setup works when I interactively open emacs and do C-c C-a.

However, when I try to generate shell using batch command :

“emacs file.sv —batch -l verilog-mode.el -f verilog-auto-inout-module”

I get following error:

“Expected 1 parameters”

Thanks a lot for your help.

Regards, Sumit

veripoolbot commented 5 years ago

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-05-30T00:29:04Z


You're missing a parenthesis in the second to last line. If you look at Messages in your interactive session you should see a similar message, it likely works because you already have another buffer with the submodule and finds it that way.

veripoolbot commented 5 years ago

Original Redmine Comment Author Name: Sumit Singh Original Date: 2019-05-30T01:02:40Z


Hi Wilson,

Thanks for your response. However, I don't think thats the issue. Looks like I made a typo while reporting it here.

To check your observation, I removed the variable part altogether and had something like following:


module example_shell (/AUTOARG/) /AUTOINOUTMODULE("example")/ endmodule

module example (***) full definition endmodule

where both shell and primary module definitions were totally inside a single file. Here also, we saw that interactively C-c C-a worked but batch command did not.

Thanks for your interest and response.

Regards, Sumit

veripoolbot commented 5 years ago

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-05-30T01:08:55Z


Ah, the correct batch line is:

emacs file.sv —batch -l verilog-mode.el -f verilog-batch-auto

(See the help page on verilog-auto for others.)

veripoolbot commented 5 years ago

Original Redmine Comment Author Name: Sumit Singh Original Date: 2019-05-30T01:25:45Z


Thanks a lot Wilson....this helped....:)

veripoolbot commented 5 years ago

Original Redmine Comment Author Name: Sumit Singh Original Date: 2019-05-30T21:22:57Z


Hi All,

In my master file which is used to create shell files, I have some 'includes which define some variable values.

To expand the 'define variables in my shell file, I used "// verilog-auto-read-includes:t" at the bottom of my shell file pre update, however when the shell file gets created I only get the port definitions with variables and content of 'include files is not used to expand the actual input or output port information.

Getting: input [`NUMBER_OF_BITS-1:0] port_in

Expecting: input [127:0] port_in

Please let me know if I need more in my setup.

Regards, Sumit

veripoolbot commented 5 years ago

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-05-30T22:42:12Z


Defines are not used for AUTOINOUTMODULE, only for filename resolution and AUTOINST/AUTOWIRE, sorry.