veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
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Use AUTO_TEMPLATE number from instance name to control string in port signalname #1452

Closed veripoolbot closed 5 years ago

veripoolbot commented 5 years ago

Author Name: David Rogoff Original Redmine Issue: 1452 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


Hi.

I'm using something like this to use the instance name to select the correct signal index for multiple instances:

logic sig1 [2];

/* mymod AUTO_TEMPLATE  "mymod_u\([0-1]\)" (
 .\(.*\)                   (\1[@]),
 );*/

mymod mymod_u0 (/*AUTOINST*/
        // Outputs
        .sig1  (sig1[0])
        );

mymod mymod_u1 (/*AUTOINST*/
        // Outputs
        .sig1  (sig1[1])
        );

This works fine. However, I have a bunch of signals that are not in the form xxx[index]. Instead, they look like

logic z_sig_even;  // goes to instance _u0
logic z_sig_odd;   // goes to instance _u1

mymod mymod_u0 (/*AUTOINST*/
        // Outputs
        .z_sig  (z_sig_even)
        );

mymod mymod_u1 (/*AUTOINST*/
        // Outputs
        .z_sig  (z_sig_odd)
        );

So, instead of using @ in the replacement string, I need a value of 0 to insert string 'even' and 1 to insert string 'odd'.

Any pointers on how to do this?

Thanks,

David

veripoolbot commented 5 years ago

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-06-01T00:46:20Z


Untested, but hopefully close enough to get you there:

/* AUTO_LISP(defun my-cell-01 () (cond ((string-match "even" vl-cell-name) 1) (t 0))) */
/* mymod AUTO_TEMPLATE (
   .\(.*\)                   (\1[@"(my-cell-01)"]),
   );*/