Closed veripoolbot closed 5 years ago
Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-06-11T21:15:23Z
Thanks for the very clear example, this makes it a lot easier.
Unfortunately Verilog-mode needs to know what is a type (as in cases without the :: it might otherwise be an interface). If you add this to Foo.sv and FooStub.sv it works, or equivalently to some startup file.
// Local Variables: // verilog-typedef-regexp: "_s$" // End:
Original Redmine Comment Author Name: Paul Donahue Original Date: 2019-06-12T00:49:48Z
Thanks for another fast response. I'm sorry to bother you since I see now that this is already documented.
Your suggestion, of course, works great.
Author Name: Paul Donahue Original Redmine Issue: 1461 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
I have this port list on a module:
I followed the recipe for generating stubs from https://www.veripool.org/projects/verilog-mode/wiki/Faq#How-do-I-make-a-Stub-module
However, verilog-mode doesn't seem to recognize FullOutput as an output:
I would expect FullOutput to be in the port list and the "output" keyword to appear in the AUTOINOUTMODULE section. In playing around, I found that it seems to work if FullOutput is declared as one of the built-in types but not when it is something else I typedef'ed.
I have attached a tarball with the Foo module, the FooStub module, a Makefile, and the verilog-mode.el I used (which is the latest from last week).
Thanks,
-Paul