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veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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AUTOINST adds outputs that aren't in module #1464

Closed veripoolbot closed 5 years ago

veripoolbot commented 5 years ago

Author Name: Shareef Jalloq Original Redmine Issue: 1464 from https://www.veripool.org

This might just be something that's not supported but I'm using some auto-generated Verilog that has multiple modules in the same file. Is that supported for AUTOs?

What I have is a single Verilog file that has 3 module definitions inside. A top level module that matches the filename and two children modules. When I run AUTOs to instantiate the top level of hierarchy, I get outputs that aren't in that module. Note that I thought this might have been a bug so updated verilog-mode to the latest and the first time I ran AUTOs it got it correct. Subsequent running seems to pull back in the incorrect outputs.

Should verilog-mode support this or will I have to post process the autogenerated code to split out the modules?

Shareef.

veripoolbot commented 5 years ago

Original Redmine Comment Author Name: Shareef Jalloq Original Date: 2019-06-13T14:24:17Z

Hmmm, there's something very fishy going on here. I've been trying to generate a testcase and that works fine. Then I went back to my original emacs and changed a few things and AUTOs couldn't "find an endmodule". So I closed and restarted emacs and it works fine with no extra outputs.

Have you tested with Emacs 26.2 yet? I just installed it.

Edit: looks like it might be something to do with how AUTOs is finding a file? Does it search in local buffers first rather than the library-directories path? I noted that after moving a Verilog file AUTOs was still looking in the old path hence the 'couldn't find endmodule' message. Is this a verilog-mode thing or an Emacs thing? Not noticed it before.

veripoolbot commented 5 years ago

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-06-14T01:17:04Z

Verilog-mode will search open buffers if it can't otherwise find a file. (This is partially so it works somewhat reasonably with unsaved changes.)

Seems like you solved your problems, so closing, feel free to add more if you still think there's problems.