Documentation bugs

[veripoolbot]

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Author Name: Paul Donahue Original Redmine Issue: 1466 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)

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I think that there are a few related bugs in the documentation. It all seems to have to do with the port names on InstModule in the examples. The output port is named "o" rather than "ov".

verilog-auto-inst says:

For example, first take the submodule InstModule.v:

    module InstModule (o,i);
       output [31:0] o;
       input i;
       wire [31:0] o = {32{i}};
    endmodule

This is then used in an upper level module:

    module ExampInst (o,i);
       output o;
       input i;
       InstModule instName
         (/*AUTOINST*/);
    endmodule

Typing \\[verilog-auto] will make this into:

    module ExampInst (o,i);
       output o;
       input i;
       InstModule instName
         (/*AUTOINST*/
          // Outputs
          .ov   (ov[31:0]),
          // Inputs
          .i    (i));
    endmodule

Where the list of inputs and outputs came from the inst module.

Note that verilog-auto will not output that. It will output something very similar but with both instances of the string "ov" replaced by "o". The last line of prose should also probably say "came from the InstModule module" or "came from InstModule".

verilog-auto-inst later says:

    InstModule instName
           (// Inputs
       .i       (my_i_dont_mess_with_it),
       /*AUTOINST*/
       // Outputs
       .ov      (ov[31:0]));

That should also say "o" instead of "ov".

verilog-auto-wire says:

An example (see `verilog-auto-inst' for what else is going on here):

    module ExampWire (o,i);
       output o;
       input i;
       /*AUTOWIRE*/
            InstModule instName
         (/*AUTOINST*/);
    endmodule

Typing \\[verilog-auto] will make this into:

    module ExampWire (o,i);
       output o;
       input i;
       /*AUTOWIRE*/
       // Beginning of automatic wires
       wire [31:0]      ov; // From inst of inst.v
       // End of automatics
       InstModule instName
         (/*AUTOINST*/
          // Outputs
          .ov   (ov[31:0]),
          // Inputs
          .i    (i));
       wire o = | ov;
    endmodule"

Same thing there but this is more complicated. There is no "ov" in the verilog-auto-inst code that is being referenced so when I run this through verilog-auto, I don't get any AUTOWIRE expansion at all. That kind of defeats the purpose of the example. The correct way to fix all of these problems is probably to rename the output on InstModule and ExampleInst in the verilog-auto-inst example to be "ov". I suspect that the ports were originally named "ov" and that these bugs and any others I may not have found yet were introduced when "ov" was renamed to "o".

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-06-15T00:42:46Z

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You're right the examples were a mess. Went through them all and made sure matched outputs.

Fixed in verilog-mode git. Keeping bug non-closed to remember to push to Emacs itself; at the moment their git server seems down.

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-06-15T12:18:51Z

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Pushed to Emacs trunk towards Emacs 27.0.