Closed veripoolbot closed 5 years ago
Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-08-01T11:00:32Z
You need to tell Verilog-Mode what are types. For example add to the end of your module and submodule files:
// Local Variables: // verilog-typedef-regexp: "^t_" // End:
Author Name: Idan Regev Original Redmine Issue: 1485 from https://www.veripool.org
Original Assignee: Wilson Snyder (@wsnyder)
verilog-mode v2019-05-06-28bee25-vpo;
package a_pkg; typedef struct packed{ logic [7:0] a; logic b; } t_a_field; endpackage
module a #(parameter A=2) ( input a_pkg::t_a_field [A-1:0] userdata //
);
using autoinst in other module: a
(
);
Result: AUTOINST of a will result of an error .a_pkg::t_a_field(a_pkg::t_a_field/.[A-1:0]/),
Current workaround Use a non packed array module a #(parameter A=2) ( input a_pkg::t_a_field userdata [A-1:0]//
);