Wrong statement continue alignment.

[veripoolbot]

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Author Name: Enze Chi Original Redmine Issue: 1495 from https://www.veripool.org

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With verilog-mode from master branch (be9b5af)

I have 3 expression as below, after press , I got wrong alignment for the example code as below:

     startc_c         <= (valid && (state == THE_START));
     end_c             <= (valid && (state == THE_END));
     valid_c           <= (valid &&
                 (state != IDLE) &&
                 (state != SKIP_DATA));

But the expected alignment should be:

     startc_c  <= (valid && (state == THE_START));
     end_c     <= (valid && (state == THE_END));
     valid_c   <= (valid &&
                          (state != IDLE) &&
                          (state != SKIP_DATA));

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-09-01T15:09:28Z

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I get:

module x;
    initial begin
       startc_c         <= (valid && (state == THE_START));
       end_c            <= (valid && (state == THE_END));
       valid_c          <= (valid &&
                            (state != IDLE) &&
                            (state != SKIP_DATA));

which seems correct. Perhaps you have some variable settings that change behavior? Please send your verilog-submit-bug-report variable dump.

[veripoolbot]

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Original Redmine Comment Author Name: Enze Chi Original Date: 2019-09-02T12:08:47Z

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Here's the variable dump

[veripoolbot]

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Original Redmine Comment Author Name: Enze Chi Original Date: 2019-09-02T12:16:02Z

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I just realise that when I call "verilog-indent-buffer", the alignment is as expected. The problem happens when press "ENTER" at the end of last line in the example code. It will align the "<=" and "!=" which it should not.

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-09-15T15:40:36Z

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Doesn't see a obvious fix; if someone would be willing to investigate further and provide a patch it would be appreciated.