Closed veripoolbot closed 5 years ago
Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-09-03T17:03:51Z
Original Redmine Comment Author Name: Ronen ddd Original Date: 2019-09-04T09:02:25Z
Wilson Snyder wrote:
Hi Wilson,
I dont want to propogate the parameters to pin, I want to propogate the parameter's value into the pin:
in the internal module we do have parameters instead of .a (a_bus[DW-1:0]) ----> .a (a_bus[15:0]
Thx, Ronen
Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2019-09-04T10:48:12Z
Ah, try this:
module InstMod ( ins, outs );
parameter WIDTH;
output [WIDTH-1:0] ins;
endmodule
module test_top;
parameter TOP_WIDTH = 3;
/* AUTO_LISP(defun my-param-range ()
(concat "[" vh-TOP_WIDTH ":0]"))*/
/* InstMod AUTO_TEMPLATE(
.WIDTH(@"vh-TOP_WIDTH"),
.ins(ins@"(my-param-range)"),
) */
InstMod mod
#(/*AUTOINSTPARAM*/
// Parameters
.WIDTH (3)) // Templated
(/*AUTOINST*/
// Outputs
.ins (ins[3:0])); // Templated
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// End:
Author Name: Ronen ddd Original Redmine Issue: 1498 from https://www.veripool.org
is it a way to use the verilog-mode to parse the instance module and use actual signal values and not parameters ? same way that it replace 'define with actual values
instead of: .rresp_0 (rresp_0[AXI_RESPW-1:0]), // Templated
use .rresp_0 (rresp_0[2:0]),
Thanks