I just found wrong indentation after SV streaming state
module test (input logic clk,
input logic a,
output logic c,
output byte d[4]);
always_ff @(posedge clk) begin
if (a == 1'b1) begin
data <= {<<byte{$urandom()}};
c <= data[1] > 8'h0f;
end
end
endmodule // test
The expected indentation should be:
module test (input logic clk,
input logic a,
output logic c,
output byte d[4]);
always_ff @(posedge clk) begin
if (a == 1'b1) begin
data <= {<<byte{$urandom()}};
c <= data[1] > 8'h0f;
end
end
endmodule // test
Author Name: Enze Chi Original Redmine Issue: 1516 from https://www.veripool.org
I just found wrong indentation after SV streaming state
The expected indentation should be: