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veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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Add rand keyword to verilog-declaration-prefix-re #16

Closed AitBits closed 6 years ago

AitBits commented 6 years ago

rand keyword also can be part of property declaration inside class definitions.

acr4 commented 6 years ago

First, thanks so much for providing pull request to improve verilog-mode!

I have reviewed this, and found that test indent_ovm.v now fails ("rand bit [127:0] data [];" indents differently from the expected value). Please review the mismatch and either (a) refine the code so the test passes or (b) confirm that the new indentation is better/more appropriate. Once 'make test' passes, please update the pull request and I'll review it again.

Also, please cross-reference this by creating a ticket on https://www.veripool.org/projects/verilog-mode/issues which serves as the official issue-tracking system for verilog-mode.

Thanks!

AitBits commented 6 years ago

@acr4 Hi, I appreciate your reply. I created corresponding ticket in issue tracker as you noted, and it contains some more details regarding this pull request.

AitBits commented 6 years ago

Closing as relevant commits were pushed.