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veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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AUTOASSIGNMODPORT and AUTOASSIGNMODPORT direction #1668

Open marmarjohnson opened 4 years ago

marmarjohnson commented 4 years ago

I've been using the AUTOINOUTMODPORT and AUTOASSIGNMODPORT to create modules that are used to build and break-out interfaces. The use is a bit different as the original intent, as I have to "flip" the modport argument to the complement of the modport (e.g. use slave vs. master and visa versa). This has been working well, but to create a monitor modport, and I don't have a complement (input instead of output).

I've included an example below. To get it to work, I've had to create an extraneous modport called "monitor_workaround" to get my compliment. Is there a way to get AUTOASSIGNMODPORT to flip the direction of the assigns to auto-generate the assigns in my case without having to generate a fake monitor_workaround modport?

example.txt

wsnyder commented 4 years ago

Perhaps you would be willing to make a pull request to implement AUTOINOUTMODPORTCOMP and AUTOASSIGNMODPORTCOMP?

Basically, make the test files, then add auto-input-modport-comp which just calls verilog-auto-inout-modport with a flag, then have that flag in verilog-auto-inout-modport swap the in/out lists.