Open marmarjohnson opened 4 years ago
Perhaps you would be willing to make a pull request to implement AUTOINOUTMODPORTCOMP and AUTOASSIGNMODPORTCOMP?
Basically, make the test files, then add auto-input-modport-comp which just calls verilog-auto-inout-modport with a flag, then have that flag in verilog-auto-inout-modport swap the in/out lists.
I've been using the AUTOINOUTMODPORT and AUTOASSIGNMODPORT to create modules that are used to build and break-out interfaces. The use is a bit different as the original intent, as I have to "flip" the modport argument to the complement of the modport (e.g. use slave vs. master and visa versa). This has been working well, but to create a monitor modport, and I don't have a complement (input instead of output).
I've included an example below. To get it to work, I've had to create an extraneous modport called "monitor_workaround" to get my compliment. Is there a way to get AUTOASSIGNMODPORT to flip the direction of the assigns to auto-generate the assigns in my case without having to generate a fake monitor_workaround modport?
example.txt