Closed engrvns closed 4 years ago
The answer is verilog-auto-output-every
Glad you found the answer in AUTOOUTPUTEVERY. I assume that worked for your use case.
Spoke too soon. AUTOOUTPUTEVERY seems to work only for AUTOWIRES. the above example does not have AUTOWIRE and does not seem to work
How do we force the signal "out" in the example to appear as a output port.
Yes, you need AUTOWIRE, in theory adding it should not hurt anything.
AUTOOUTPUTS are normally inferred out of "non-internally" connected instance outputs. Is there any way one could write a AUTO to force creation of output ports based of internal signal names.
One usage for this for this when you want to width-cast an instance output before it gets connected to a module output. This forces the user to create an internal signal.
Simplistic Example: module top (output [3:0] out ...);
/out AUTO_TEMPLATE ( .out (temp_out[]), );/
assign out = `4(temp_out); //Width casting forces internal signal
inst inst ( .out(temp_out[1:0)) ... ); endmodule