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veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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How to write a AUTO rule for creating AUTOOUTPUTS of internal signals #1669

Closed engrvns closed 4 years ago

engrvns commented 4 years ago

AUTOOUTPUTS are normally inferred out of "non-internally" connected instance outputs. Is there any way one could write a AUTO to force creation of output ports based of internal signal names.

One usage for this for this when you want to width-cast an instance output before it gets connected to a module output. This forces the user to create an internal signal.

Simplistic Example: module top (output [3:0] out ...);

/out AUTO_TEMPLATE ( .out (temp_out[]), );/

assign out = `4(temp_out); //Width casting forces internal signal

inst inst ( .out(temp_out[1:0)) ... ); endmodule

engrvns commented 4 years ago

The answer is verilog-auto-output-every

wsnyder commented 4 years ago

Glad you found the answer in AUTOOUTPUTEVERY. I assume that worked for your use case.

engrvns commented 4 years ago

Spoke too soon. AUTOOUTPUTEVERY seems to work only for AUTOWIRES. the above example does not have AUTOWIRE and does not seem to work

How do we force the signal "out" in the example to appear as a output port.

wsnyder commented 4 years ago

Yes, you need AUTOWIRE, in theory adding it should not hurt anything.