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veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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Auto declaration of undeclared signals that can not be generated by AUTOWIRE and AUTOREG #1670

Closed guoqinglei closed 4 years ago

guoqinglei commented 4 years ago

Is there any demands on auto declaration of undeclared signals, i.e.,

input a, d;
output c;

/*AUTODECLARE*/
assign b = a;
assign c = b + d;

Here, how to auto generate following codes ?

input a, d;
output c;

/*AUTODECLARE*/
wire b;
wire c;

assign b = a;
assign c = b + d;
wsnyder commented 4 years ago

Thanks for checking, but Verilog-mode is generally driven by declarations and as assign is not a declaration there is no AUTO to make these into an output. If you can instead use "wire b = a" you could then use AUTOOUTPUTEVERY.