Closed Haim68 closed 4 years ago
Thanks for your report.
Verilog-mode does not parse generate for loops as it cannot perform elaboration as the parameters can have any value. YNote also AUTOOUTPUT looks only at submodule outputs, so your wire declaration won't have an effect. You'll need to manually declare any outputs/wires from your loop, sorrt.
BTW there's no need for the AUTO_TEMPLATE to be inside the for loop, only the instantiation (which you didn't show but presumably is there) needs to be. No harm to leave it, but might be easier to read outside.
Hello I declare: logic [WIDTH-1:0] sig1;
In the code I use generate to connect the signal to 1 bit output port of "WIDTH" number of sub-module instantiations: generate for (genvari=0; i<WIDTH;i++) begin: i_loop / my_inst AUTO_TEMPLATE( .sig1 (sig1[i]), ) /
The issue is that the AUTOOUTPUT generate the following output port: output [i] sig1, Instead of: output [WIDTH-1:0] sig1,
How can I overcome this issue? Thanks!!