AUTOWIRE declares array of typedef as signal

veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

http://veripool.org/verilog-mode

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Closed imgod2u closed 4 years ago

imgod2u commented 4 years ago

One of my outputs is a typedef (defined in a package) of the form:

typedef logic [`DATA_WID-1:0] data_t;

I've created an array of these as an output to one of my modules:

module sub_unit( input logic clk, input logic rst, output data_t [3:0] values );

At the top level, AUTOWIRE will declare this as a wire: logic data_t [`DATA_WID-1:0]; logic values;

wsnyder commented 4 years ago