Closed vinamarora8 closed 4 years ago
This is how a sample source now looks (with gruvbox)
Currently this doesn't support declaration statements spanning multiple lines. That apparently would take a lot more work and I'm looking into it. For now, this works well for single line declarations and will be good enough for majority of cases.
Aims at solving issue https://github.com/veripool/verilog-mode/issues/1677