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veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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Module name not highlighted unless followed by '(' on the same line #1679

Closed vinamarora8 closed 4 years ago

vinamarora8 commented 4 years ago

Of these 2 ways to start a module definition:

module exampleMod(clk, rst...);

module exampleMod
   #(parameter A = 10)
    (input clk, 
     input rst
     );

module's name is highlighted with font-lock-function-name-face only in the first case.

vinamarora8 commented 4 years ago

Turns out it was because of simple syntax issue. Addressed in #1680

wsnyder commented 4 years ago

Thanks for the pull request, much appreciated. The git log needs a special format to appease Emacs so pushed manually.