wront indentation on constraints

[luisgutz]

The closing brace of an constraint block is not recognize as finishing the indentation, and they keep piling up.

This is how it looks:

class alarmCfgC;
  rand bit [15:0] v1;
  rand bit [15:0] v2;
  rand bit [1:0] c1;

  constraint c1 { (c1 == 'b00  ) -> (v1  < v2);
    (c1 == 'b01 ) -> (v1  > v2);
    (c1 == 'b10) -> (v1 == v2);}
    constraint c1 { (c1 == 'b00  ) -> (v1  < v2);
      (c1 == 'b01 ) -> (v1  > v2);
      (c1 == 'b10) -> (v1 == v2);}

      endclass // alarmCfgC

and this is what I was expecting:

class alarmCfgC;
  rand bit [15:0] v1;
  rand bit [15:0] v2;
  rand bit [1:0] c1;

  constraint c1 { (c1 == 'b00  ) -> (v1  < v2);
    (c1 == 'b01 ) -> (v1  > v2);
    (c1 == 'b10) -> (v1 == v2);}
constraint c1 { (c1 == 'b00  ) -> (v1  < v2);
  (c1 == 'b01 ) -> (v1  > v2);
  (c1 == 'b10) -> (v1 == v2);}

endclass // alarmCfgC

I can see that '{' is the first element in verilg-indent-re const, but I cannot find where the end of indentation is calculated, and adding the closing brace "}" next to it seems to have no effect

[acr4]

Indention works for me with both versions 2020-02-23-dddb795-vpo-GNU and 2020-06-27-0da9923-vpo-GNU. What version are you using (C-h v verilog-mode-version RET)?

[luisgutz]

I'm on 2002.02.23 (436). I'll update to the latest.

On Thu, 16 Jul 2020, 14:57 Alex Reed, notifications@github.com wrote:

Indention works for me with both versions 2020-02-23-dddb795-vpo-GNU and 2020-06-27-0da9923-vpo-GNU. What version are you using (C-h v verilog-mode-version RET)?

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/veripool/verilog-mode/issues/1685#issuecomment-659429979, or unsubscribe https://github.com/notifications/unsubscribe-auth/AAC57YRHZ4IWWOWIU533Q6TR34BNRANCNFSM4O4A5PXQ .

[luisgutz]

so Emacs was loading a far older version. When using the latest from github, the constraints are correctly indented.

I would close this ticket, but I don't think I can.