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veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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do we support macro definition in port list #1688

Closed zjuxieyi closed 3 years ago

zjuxieyi commented 3 years ago

Hi,

I'm doing a third-party IP integration and using EMACS-verilog-mode.

This third-party IP using this bad coding-style in its top file, like this: `ifdef A_EN

input[31:0] a_addr; input a_valid; output a_ready;

`elsif

...

`endif

But in any one of my macro-definition header files, I have not defined this macro "A_EN" at all. Via EMACS-verilog-mode, if I create a wrapper file to include this third-party IP's RTL-top，and other my own RTL modules. I still see that these ports on the port list in my wrapper. However these ports are not expected to present (if specifying correct macro):

Is there a way to fix this, let EMACS to correctly present the right port pins according to my macro-definitions.

Thanks, Alex

wsnyder commented 3 years ago

See https://github.com/veripool/verilog-mode/blob/master/FAQ.adoc#why-do-the-autos-ignore-my-ifdefs