AUTOINST doesn’t seem to work with AUTOINOUTMODULE

[scdemarc]

// Observed issue: // A shell-module having a port list expanded with /*AUTOINOUTMODULE/ // does not appear to have it's instantiation expanded with /*AUTOINST/ // The /*AUTOINST*/ above appears remain unexpanted. // The following generic example demonstrates the issue.

module design_module

(

parameter WIDTH = 8, parameter NUM_CHANNELS = 4, ) ( input clk, resetn, input [NUM_CHANNELS-1:0][WIDTH-1:0] data_in, output [NUM_CHANNELS-1:0][WIDTH-1:0] data_out ); endmodule

module dv_checker #( parameter WIDTH = 8, parameter NUM_CHANNELS = 4, ) ( /*AUTOINOUTMODULE("design_module","","^input")*/ // Beginning of automatic in/out/inouts (from specific module) input clk, input resetn, input [NUM_CHANNELS-1:0] [WIDTH-1:0] data_in // End of automatics ); endmodule

module tb_top();

dv_checker Idv_checker(/*AUTOINST*/);

endmodule

[wsnyder]

Verilog-mode generally works best if you have only a single module per file. If you do it that way, then expand bottom-to-top, it works correctly as expected, that is changing the list in one buffer then re-autoing tb_top in another buffer picks up the right I/O.

Unfortunately I looked at fixing this and don't see a fix for this that wouldn't break a lot of other things, it's a result of the order of how they are expanded, so unfortunately we'll need to live with this.