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Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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how to use AUTOOUTPUT #1696

Closed zjuxieyi closed 4 years ago

zjuxieyi commented 4 years ago

Hi,

Is my understanding of AUTOOUTOUT and AUTOWIRE wrong ?

module top (

/*AUTOINPUT
/*AUTOOUTPUT*/
);

/*AUTOWIRE*/

sub1 u_sub1 (
  .in (sub1_in),
  .out1( internal1),
  .out2( internal2),
 ...
);

sub2 u_sub2 (
  .in1( internal1),
  .in2( internal2),
  .out( sub2_out),
 ...
);

endmodule

But after verilog-mode, I get this result, I these internal1 & internal2 are on top module's output lists.

module top (
...
output internal1,
output internal2,
...
/*AUTOINPUT
/*AUTOOUTPUT*/
);

/*AUTOWIRE*/

sub1 u_sub1 (
  .in (sub1_in),
  .out1( internal1),
  .out2( internal2),
 ...
);

sub2 u_sub2 (
  .in1( internal1),
  .in2( internal2),
  .out( sub2_out),
 ...
);

endmodule
wsnyder commented 4 years ago

You need // Input and // Output comments in your pin connections.

"Also note that any signals before the AUTOINST will only be picked up by AUTOWIRE if you have the appropriate // Input or // Output comment, and exactly the same line formatting as AUTOINST itself uses.