and the wrapping results from some code at the end of verilog-auto-inst (link).
If you use the default value for verilog-cexp-indent the alignment is consistent across both indent-region and verilog-auto-inst. If verilog-auto-inst could be coerced to reuse the logic of verilog-indent-line-relative that should resolve the first issue.
Is there a reason the code pulls the closing parenthesis and semicolon to the end of the final port?
I'm running the latest commit (03ac87a).
If I set
verilog-cexp-indent 2
and indent the code withindent-region
(which usesverilog-indent-line-relative
under the hood I believe), I get:If I subsequently run
verilog-auto
the indentation oninst_example
changes:There are two issues as far as I can see:
/*AUTOINST*/
behind)I took a look at the code and the first behavior is the result of this line in
verilog-auto-inst
(link):and the wrapping results from some code at the end of
verilog-auto-inst
(link).If you use the default value for
verilog-cexp-indent
the alignment is consistent across bothindent-region
andverilog-auto-inst
. Ifverilog-auto-inst
could be coerced to reuse the logic ofverilog-indent-line-relative
that should resolve the first issue.Is there a reason the code pulls the closing parenthesis and semicolon to the end of the final port?
Cheers