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veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
http://veripool.org/verilog-mode
GNU General Public License v3.0
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#1163: fix for instance port indention inside generate for loop #1699

Closed ruelparent closed 3 years ago

wsnyder commented 3 years ago

Hmm, seems like patch this wasn't based off master. Anyways I merged it manually, thanks for the contribution.

ruelparent commented 3 years ago

Sorry about not finishing the change properly. I had a free weekend and I thought it was good but when the regression had a failure I never had another free moment. Well at least while I was motivated to do something about it. Thanks for your time and effort in maintaining the mode.

On Thu, Sep 16, 2021 at 8:01 AM Wilson Snyder @.***> wrote:

Hmm, seems like patch this wasn't based off master. Anyways I merged it manually, thanks for the contribution.

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