indent wrong if within and ifdef else block

[jlechnar]

Hello,

in the following code the indent is wrong - see ISSUE comment. Please also find attached a minimum example.

BR, Joachim

`ifdef TEST
   foo1 bar
`else
     foo2 bar // ISSUE: indent wrong, should be like for foo1 bar !
`endif
       (/*AUTOINST*/);

ifdef_instance.tar.gz

[wsnyder]

Verilog-mode can't really handle all the possible ifdef combinations so this is unlikely to get fixed; furthermore it will confuse the AUTOs. I suggest instead this syntax:

`ifdef TEST
 `define BAR_INST foo1
`else
 `define BAR_INST foo2
`endif
   `BAR_INST bar
     (/*AUTOINST*/
      // Inputs
      .signal                         (signal));

endmodule

// Local Variables:
// eval:(verilog-read-defines)
// End:

[acr4]

I agree with Wilson. Stylistically this s is also a lot easier to read. It sets up the intent (pick a different module type based on configuration) and separates it from the boring language mechanics.

Sent from my iPhone

On Jan 23, 2021, at 10:54, Wilson Snyder notifications@github.com wrote:

 Verilog-mode can't really handle all the possible ifdef combinations so this is unlikely to get fixed; furthermore it will confuse the AUTOs. I suggest instead this syntax:

ifdef TEST define BAR_INST foo1 else define BAR_INST foo2 endif BAR_INST bar (/AUTOINST/ // Inputs .signal (signal));

endmodule

// Local Variables: // eval:(verilog-read-defines) // End: — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub, or unsubscribe.

[jlechnar]

Thanks for the suggested syntax that works also for me.